The present invention relates to the formation of semiconductor devices. More specifically, the invention relates to the etching of high aspect ratio features for semiconductor devices.
During semiconductor wafer processing, in 3D flash memory devices, multiple cells are stacked up together in chain format to save space and increase packing density.
This application is related to U.S. Pat. No. 9,018,103, entitled “HIGH ASPECT RATIO ETCH WITH COMBINATION MASK” issued on Apr. 28, 2015 and U.S. Pat. No. 9,659,783, entitled “HIGH ASPECT RATIO ETCH WITH COMBINATION MASK” issued on May 23, 2017, which are both incorporated by reference for all purposes, describe processes for etching high aspect ratio features in stacks.